This invention relates to a source line high voltage driver circuit and more particularly, to a source line high voltage driver circuit for a semiconductor memory device having improved reliability and read performance relative to prior high voltage driver circuits.
Semiconductor memory devices typically include several memory cells, each having a control gate, a floating gate for storing electrical charge, effective to allow the cells to be programmed, a drain terminal and a source terminal.
In a conventional memory device, a word line is connected to the respective control gates of the memory cells, a bit line is coupled to the respective drain terminals of the memory cells, and a source line is coupled to the respective source terminals of the memory cells. Driver circuits are employed to selectively drive and/or place different voltages on the various lines in order to perform reading and programming or writing functions.
One type of driving circuit, commonly referred to as a high voltage source line driver, is used to drive a source line during read and program/write functions. For example and without limitation, this type of circuit connects the source line to a relatively high voltage (e.g., ten volts) during program erase functions. The circuit must, however, also be capable of providing read functions. Prior source line driver circuits typically include a convention latching circuit employing p-type and n-type metal-oxide-semiconductor (xe2x80x9cMOSxe2x80x9d) transistors. One problem with these conventional source line driver circuits is that the relatively high voltage received, supplied and discharged by the circuit during program cycles can damage the transistors of the circuit over time.
Efforts have been made to include additional transistors within these source line driver circuits in order to isolate the high voltage encountered during program erase cycles to avoid damage to the circuit. One of these prior source line driver circuits utilizes a pair of nMOS transistors arranged in a cascode structure to provide protection to the circuit.
Referring now to FIG. 1, there is shown a schematic diagram illustrating a source line high voltage activated driver circuit 10 which utilizes a cascode structure to avoid damage to the circuit 10. Particularly, circuit 10 includes high voltage nMOS transistors M1 and M2 which are arranged in a serial cascode structure. When a program erase function is desired, signal lines WL and PROG are set xe2x80x9chighxe2x80x9d (i.e., set to a voltage representing a positive logic value), thereby activating transistors 1 and 2 and causing node N0 to be xe2x80x9clowxe2x80x9d (i.e., to have a voltage representing a negative logic value). As a result, p-type MOS transistor P1 is activated and the high voltage signal (e.g., approximately ten volts) at the source of transistor P1 is communicated to node N1 and source line SL. Program line PROG_L is set low and the serial cascode structure of transistors M1 and M2 provide isolation to transistors M3 and MN from the high voltage signal, thereby avoiding damage to the circuit 10 and improving the reliability of circuit 10 relative to prior source line driver circuits.
However, the circuit 10 suffers from some drawbacks. During a read function, source line SL must be discharged and connected to ground (i.e., the high voltage at node N1 must be discharged to ground). Particularly, during a read cycle, signal line PROG_L is set high, the sources of p-type transistors P1 and P2 are coupled to a predetermined voltage (Vcc), and the existing voltage at node N1 is discharged through the series cascode structure M1, M2 along discharge path 12. In the read cycle, if M1, M2 is small, the resulting conduction is relatively poor, thus the effective cell current will be small and the read performance will be worse. Because transistors M1 and M2 are relatively large and are connected in series, the conduction between source line SL and ground is decreased, and the read performance of circuit 10 is degraded. Furthermore, due to the large number of driver circuits in a typical semiconductor memory device, the increased size of the circuit undesirably and significantly increases the overall size of the device.
There is therefore a need for a new and improved source line high voltage driver circuit having improved durability relative to prior circuits, while maintaining and/or improving the read performance of the circuit.
A first non-limiting advantage of the invention is that it provides a source line high voltage driver circuit which has improved durability and read performance relative to prior circuits of the same size.
A second non-limiting advantage of the invention is that it provides a source line high voltage driver circuit which has improved conduction between the source line and ground relative to prior circuits.
According to a first aspect of the present invention, a source line driver circuit is provided and includes a source line, a first circuit portion which is electrically coupled to the source line and which is effective to selectively provide a high voltage signal to the source line during a write cycle; and a cascode circuit portion which is electrically coupled to the source line and which includes a first transistor, and a plurality of second transistors which are disposed in a parallel relationship to each other, the cascode circuit portion being effective to selectively xe2x80x9cground the sourcexe2x80x9d during a read cycle.
According to a second aspect of the present invention, a high voltage source line driver circuit is provided. The circuit includes a latching circuit which selectively provides a high voltage signal to the source line during a write cycle; a cascode circuit which is coupled to the source line and which includes a first transistor which is coupled to the source line and which includes a first gate, a second transistor which is coupled to the first transistor and which includes a second gate, and a plurality of third transistors which are disposed in parallel with the second transistor; and at least one control signal which is coupled to the first and second gates and which is effective to selectively activate the first and second transistors during a read cycle, thereby discharging the source line.
According to a third aspect of the present invention, a method of driving a plurality of source lines within a memory device is provided. The method includes the steps of: providing a plurality of latching circuits for selectively applying a high voltage to the plurality of source lines; providing a plurality of cascode circuits which are each coupled to a unique one of the plurality of source lines, and which each includes a first transistor and a second transistor which are selectively activated to selectively discharge the plurality of source lines; and electrically coupling each of the second transistors together in a parallel relationship, thereby causing the second transistors to form a virtual ground potential.
These and other features, advantages, and objects of the invention will become apparent by reference to the following specification and by reference to the following drawings.